V

V

Bit Stream:

Mean Output:

Instructions The diagram inside the applet shows a basic first order sigma-delta modulator. More sophisticated parts may have multiple modulators and integrators however these tend to obscure the underlying sigma-delta principle. The input voltage V The stream of 1's and 0's is subsequently digitally filtered (not shown) to produce a slower stream of multi-bit samples. The sigma-delta modulator loop typically runs at a much higher frequency than the final output rate of the digital filter. For example, a converter with a 2kHz output data rate may have a modulator loop frequency of over 2.5MHz. Enter an ADC reference voltage in the lower input field. The ADC will convert input voltages that fall between +/- V Enter the voltage to be converted in the V Click the To see the outputs at the previous step of the tutorial, click the To advance the tutorial 512 complete loops of the modulator, click the Example Let V The outputs from the comparator will be: 1, 0, 1, 1, 1, 0, 1, 1. This means 6 of the 8 outputs have been a 1; i.e. output is 75% of fullscale. The allowed input range is -2.5 to +2.5 (+/-V With a 1.0V input the input is 3.5V above the bottom of the 5.0V span or 70% of fullscale. If we continue looping, the ones density of the above output stream will get closer and closer to 70%. The digital filter does a much better job at detecting this trend then our simple count ones method. |

Related Information AN-607: Selecting a Low Bandwidth Sigma-Delta ADC |